SH7727 Datasheet, PDF (507/1109 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperH RISC engine Family/SH7700 Series

Section 14 Direct Memory Access Controller (DMAC)
Compare-Match Constant Register 0 (CMCOR0)
The compare-match constant register 0 (CMCOR0) is a 16-bit register that sets the period until a
compare-match of CMCNT0 and CMCOR0 occurs.
The CMCOR0 is initialized to H'FFFF by a reset, but it retains its previous values in standby
mode.
Bit: 15
14
13
12
11
10
9
8
Initial value: 1
1
1
1
1
1
1
1
R/W: R/W R/W R/W R/W R/W R/W R/W R/W
Bit: 7
6
5
4
3
2
1
0
Initial value: 1
1
1
1
1
1
1
1
R/W: R/W R/W R/W R/W R/W R/W R/W R/W
14.4.3 Operation
Period Count Operation
When the clock is selected with the CKS1 and CKS0 bits in CMCSR0 and the STR0 bit in
CMSTR is set to 1, the CMCNT0 starts incrementation with the selected clock. When the
CMCNT value matches that in CMCOR0, CMCNT0 is cleared to H'0000 and the CMF flag in
CMCSR0 is set to 1. The CMCNT0 counter starts incrementation again from H'0000.
Figure 14.27 shows the compare-match counter operation.
CMCNT0 value
CMCOR0
Counter cleared by
CMCOR0 compare match
H'0000
Figure 14.27 Counter Operation
Time
Rev. 5.00 Dec 12, 2005 page 435 of 1034
REJ09B0254-0500