SH7727 Datasheet, PDF (1047/1109 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperH RISC engine Family/SH7700 Series

Section 32 Electrical Characteristics
32.3.8 Peripheral Module Signal Timing
Table 32.11 Peripheral Module Signal Timing
Conditions: VccQ = 2.6 to 3.6 V, Vcc = 1.60 to 2.05 V, AVcc = 3.3 ± 0.3 V, Ta = –20 to 75°C
Module Item
Symbol Min
Max
RTC
Oscillation settling time
tROSC
—
3
SCI
Input clock Asynchronization
tSCYC
4
—
cycle
Clock synchronization
6
—
Input clock rise time
Input clock fall time
Input clock pulse width
Transmission data delay time
Receive data setup time
(clock synchronization)
tSCKR
—
1.5
tSCKF
—
1.5
tSCKW
0.4
0.6
tTXD
—
100
tRXS
100
—
Receive data hold time
(clock synchronization)
tRXH
100
—
RTS delay time
CTS setup time
(clock synchronization)
tRTSD
—
100
tCTSS
100
—
CTS hold time
(clock synchronization)
tCTSH
100
—
Port
Output data delay time
tPORTD
Input data setup time (1)
tPORTS1
Input data hold time (1)
tPORTH1
Input data setup time (2)
tPORTS2
Input data hold time (2)
tPORTH2
Input data setup time (3)
tPORTS3
Input data hold time (3)
tPORTH3
DMAC DREQ setup time
tDRQS
DREQ hold time
tDREQH
DRAK delay time
tDRAKD
Note: * Pcyc stands for “peripheral clock (Pφ) cycle.”
—
26
15
—
8
—
tcyc + 15 —
8
—
3 tcyc + 15 —
8
—
8
—
8
—
—
14
Unit
s
Pcyc*
Pcyc*
Figure
32.41
32.42
32.43
32.42
tScyc
ns 32.43
ns 32.44
ns 32.45
32.46
Rev. 5.00 Dec 12, 2005 page 975 of 1034
REJ09B0254-0500