SH7727 Datasheet, PDF (285/1109 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperH RISC engine Family/SH7700 Series

Section 8 User Break Controller
8.2.8 Break Bus Cycle Register B (BBRB)
Bit: 15 14 13 12 11 10 9
8
7
6
5
4
3
2
1
0
— — — — — — XYE XYS CDB1 CDB0 IDB1 IDB0 RWB1 RWB0 SZB1 SZB0
Initial value: 0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
R/W: R
R
R
R
R
R R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W
Break bus cycle register B (BBRB) is a 16-bit read/write register, which specifies (1) logic or
internal bus (L or I bus), X bus, of Y bus, (2) CPU cycle or DMAC cycle, (3) instruction fetch or
data access, (4) read/write, and (5) operand size in the break conditions of channel B. A power-on
reset initializes BBRB to H'0000.
Bits 15 to 10—Reserved: These bits are always read as 0. The write value should always be 0.
Bit 9—X/Y Memory Bus Enable (XYE): Selects the logic bus or internal bus (L bus or I bus) or
the X/Y memory bus as the bus of the channel B break condition.
Bit 9: XYE
0
1
Description
Select internal bus (I bus) for the channel B break condition
Select X/Y memory bus (X/Y bus) for the channel B break condition
Bits 8—X or Y Memory Bus Select (XYS): Selects the X bus or the Y bus as the bus of the
channel B break condition.
Bit 8: XYS
0
1
Description
Select the X bus for the channel B break condition
Select the Y bus for the channel B break condition
Bits 7 and 6—CPU Cycle/DMAC Cycle Select B (CDB1 and CDB0): Select the CPU cycle or
DMAC cycle as the bus cycle of the channel B break condition.
Bit 7: CDB1 Bit 6: CDB0
0
0
*
1
1
0
Note: * Don’t care.
Description
Condition comparison is not performed
The break condition is the CPU cycle
The break condition is the DMAC cycle
(Initial value)
Rev. 5.00 Dec 12, 2005 page 213 of 1034
REJ09B0254-0500