SH7727 Datasheet, PDF (542/1109 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperH RISC engine Family/SH7700 Series

Section 16 Realtime Clock (RTC)
Bit 3—Alarm Interrupt Enable Flag (AIE): Enables or disables interrupt generation when the
alarm flag (AF) is set to 1.
Bit 3: AIE
0
1
Description
An alarm interrupt is not generated when the AF flag is set to 1
An alarm interrupt is generated when the AF flag is set to 1
(Initial value)
Bit 0—Alarm Flag (AF): The AF flag is set to 1 when the alarm time set in alarm registers (only
for the registers with ENB bit set to 1) match the clock and calendar time. This flag is cleared to 0
when 0 is written, but the previous value is retained when 1 is to be written.
Bit 0: AF
Description
0
Clock/calendar and alarm register have not matched since last reset to 0.
Clearing condition: When 0 is written to AF
(Initial value)
1
Setting condition: Clock/calendar and alarm register have matched (only for the
registers with ENB set to 1)*
Note: * The value is not modified when 1 is written to AF.
16.2.16 RTC Control Register 2 (RCR2)
The RTC control register 2 (RCR2) is an 8-bit read/write register that controls periodic interrupts,
30-second adjustment ADJ, divider circuits RESET, and starting and stopping of the RTC count. It
is initialized to H'09 by a power-on reset. By a manual reset, bits except RTCEN and START are
initialized. RCR2 is not initialized and retains its contents in standby mode.
Bit: 7
PEF
Initial value: 0
R/W: R/W
6
5
4
3
2
1
0
PES2 PES1 PES0 RTCEN ADJ RESET START
0
0
0
1
0
0
1
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Rev. 5.00 Dec 12, 2005 page 470 of 1034
REJ09B0254-0500