SH7727 Datasheet, PDF (20/1109 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperH RISC engine Family/SH7700 Series

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759 25.1.1 Features
• Supports 1/2/4/8/15/16-bpp (bit per pixel) • Supports 4/8/15/16-bpp (bit per pixel)
color modes
color modes
• Supports 1/2/4-bpp grayscale modes
• Supports 1/2/4/6-bpp grayscale modes
760 Figure 25.1 Block Diagram
CKIO
Bus clock (Bφ)
P clock
Peripheral clock (Pφ)
762 Table 25.2 Register Configuration
H'F606
H'F60F
763 25.2.1 LCDC Input Clock Register
(LDICKR)
This LCDC can select CKIO (bus clock),
the P clock, or the external clock as its
operation clock source. …
This LCDC can select the bus clock (Bφ),
the peripheral clock (Pφ), or the external
clock as its operation clock source. …
Bits 13, and 12Input Clock Select
(ICKSEL1 and ICKSEL0):
CKIO is selected
Bus clock (Bφ) is selected
P clock is selected
Peripheral clock (Pφ) is selected
766 25.2.2 LCDC Module Type Register
(LDMTR)
Bits 5 to 0—Module Interface Type Select
(MIFTYP5 to MIFTYP0):
If an STN or DSTN panel is selected,
display control is performed using a 24-bit
space-modulation FRC consisting of the 8-
bit R, G, and B included in the LCDC, …
If an STN or DSTN panel is selected,
display control is performed using a 24-bit
space-modulation FRC (Frame Rate
Controller) consisting of the 8-bit R, G, and
B included in the LCDC, …
783 25.2.17 LCDC Power Management Mode
Register (LDPMMR)
Bit 4DON Pin Enable (DONE):
Bit 4
DONE
0
1
Description
Disabled: DON pin is masked and fixed low
(Initial value)
Enabled: DON pin output is asserted and negated according to the power-on or power-
off sequence
Bit 4
DONE
0
1
Description
Disabled: DON pin is masked and fixed low
Enabled: DON pin output is asserted and negated according to the power-on or power-
off sequence
(Initial value)
784
25.2.18 LCDC Power-Supply Sequence
Period Register (LDPSPR)
Bit: 15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
ONA3 ONA2 ONA1 ONA0 ONB3 ONB2 ONB1 ONB0 OFFE3 OFFE2 OFFE1 OFFE0 OFFF3 OFFF2 OFFF1 OFFF0
Initial value: 0
0
0
0
0
0
0
0
0
0
0
1
0
0
0
0
R/W: R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W
Bit: 15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
ONA3 ONA2 ONA1 ONA0 ONB3 ONB2 ONB1 ONB0 OFFE3 OFFE2 OFFE1 OFFE0 OFFF3 OFFF2 OFFF1 OFFF0
Initial value: 1
1
1
1
0
1
1
0
0
0
0
0
1
1
1
1
R/W: R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W
Rev. 5.00 Dec 12, 2005 page xx of lxxii