SH7727 Datasheet, PDF (368/1109 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperH RISC engine Family/SH7700 Series

Section 12 Bus State Controller (BSC)
Bits 4 to 2—Area 2, Area 3 Memory Type (DRAMTP2, DRAMTP1, DRAMTP0): Designate
the types of memory connected to physical space areas 2 and 3. Ordinary memory, such as ROM,
SRAM, or flash ROM, can be directly connected. Synchronous DRAM can also be directly
connected.
Bit 4: DRAMTP2 Bit 3: DRAMTP1 Bit 2: DRAMTP0 Description
0
0
0
Areas 2 and 3 are ordinary memory
(Initial value)
1
Reserved (Setting disabled)
1
0
Area 2: ordinary memory;
Area 3: synchronous DRAM^*1
1
Areas 2 and 3 are synchronous
DRAM^{*1 *2}
1
0
0
Reserved (Setting disabled)
1
Reserved (Setting disabled)
1
0
Reserved (Setting disabled)
1
Reserved (Setting disabled)
Notes: 1. When selecting this mode, set the same bus width for area 2 and area 3.
2. If clock rate is specified as 1φ : Bus clock = 1:1 , synchronous DRAM cannot be
accessed.
Bit 1—Area 5 Bus Type (A5PCM): Designates whether to access physical space area 5 as
PCMCIA space.
Bit 1: A5PCM
0
1
Description
Access physical space area 5 as ordinary memory
Access physical space area 5 as PCMCIA space
(Initial value)
Bit 0—Area 6 Bus Type (A6PCM): Designates whether to access physical space area 6 as
PCMCIA space.
Bit 0: A6PCM
0
1
Description
Access physical space area 6 as ordinary memory
Access physical space area 6 as PCMCIA space
(Initial value)
Rev. 5.00 Dec 12, 2005 page 296 of 1034
REJ09B0254-0500