SH7727 Datasheet, PDF (464/1109 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperH RISC engine Family/SH7700 Series

Section 14 Direct Memory Access Controller (DMAC)
Bit 6—DREQ Select (DS): DS selects the sampling method of the DREQ pin that is used in
external request mode is detection in low level or at the falling edge.
This bit is only valid in CHCR0. This bit in CHCR1, CHCR2 and CHCR3 is always read as 0 and
should only be written with 0.
Also, it should be cleared to 0 (low-level detection) if an on-chip supporting module is specified as
a transfer request source in channel 0.
Bit 6: DS
0
1
Description
DREQ detected in low level
DREQ detected at falling edge
(Initial value)
Bit 5—Transmit Mode (TM): TM specifies the bus mode when transferring data.
Bit 5: TM
0
1
Description
Cycle steal mode
Burst mode
(Initial value)
Bits 4 and 3—Transmit Size 1, 0 (TS1 and TS0): TS1 and TS0 specify the size of data to be
transferred.
Bit 4: TS1
0
0
1
1
Bit 3: TS0
0
1
0
1
Description
Byte size (8 bits)
Word size (16 bits)
Longword size (32 bits)
16-byte unit (4 longword transfers)
(Initial value)
Bit 2—Interrupt Enable (IE): Setting this bit to 1 generates an interrupt request when the
number of times of data transfers specified with DMATCR has completed (TE = 1).
Bit 2: IE
0
1
Description
Interrupt request is not generated even when data transfer ends by the
specified count
(Initial value)
Interrupt request is generated when data transfer ends by the specified count
Rev. 5.00 Dec 12, 2005 page 392 of 1034
REJ09B0254-0500