SH7727 Datasheet, PDF (469/1109 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperH RISC engine Family/SH7700 Series

Section 14 Direct Memory Access Controller (DMAC)
Bit 2—Address Error Flag (AE): AE indicates that an address error occurred during DMA
transfer. If this bit is set during data transfer, transfers on all channels are suspended. The CPU
cannot write 1 to this bit. This bit can only be cleared by writing of 0 after reading of 1.
Bit 2: AE
0
1
Description
No DMAC address error. DMA transfer is enabled.
(Initial value)
Clear conditions: When this bit is written with 0 after it is read as 1
By a power-on reset
By a manual reset
DMAC address error. DMA transfer is disabled.
Setting condition: When a DMAC address error occurred
Bit 1—NMI Flag (NMIF): NMIF indicates that an NMI interrupt occurred. This bit is set both in
operating state and in halt state. The CPU cannot write 1 to this bit. This bit can only be cleared
by writing of 0 after reading of 1.
Bit 1: NMIF
0
1
Description
No NMI input. DMA transfer is enabled.
(Initial value)
Clear conditions: When this bit is written with 0 after it is read as 1
By a power-on reset
By a manual reset
NMI input. DMA transfer is disabled.
Setting condition: When an NMI interrupt is generated
Bit 0—DMA Master Enable (DME): DME enables or disables DMA transfer for all channels. If
the DME bit and the DE bit corresponding to each channel in CHCR are set to 1, transfer is
enabled in the corresponding channel. If this bit is cleared during transfer, transfer in all the
channels can be terminated.
Even if the DME bit is set, transfer is not enabled when the TE bit is 1 or the DE bit is 0 in CHCR,
or the NMIF bit is 1 in DMAOR.
Bit 0: DME
0
1
Description
Disable DMA transfer for all channels
Enable DMA transfer for all channels
(Initial value)
Rev. 5.00 Dec 12, 2005 page 397 of 1034
REJ09B0254-0500