SH7727 Datasheet, PDF (470/1109 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperH RISC engine Family/SH7700 Series

Section 14 Direct Memory Access Controller (DMAC)
14.3 Operation
When a DMA transfer request is generated, the DMAC starts the transfer according to the
predetermined channel priority order. When a transfer end condition is satisfied, it ends the
transfer. Three types of transfer requests can be, auto request, external request, and on-chip
module request. For the dual address mode, the direct address transfer mode and indirect address
transfer mode are supported. For the bus mode, the burst mode or the cycle steal mode can be
selected.
14.3.1 DMA Transfer Flow
When transfer conditions have been set to the DMA source address registers (SAR), DMA
destination address registers (DAR), DMA transfer count registers (DMATCR), DMA channel
control registers (CHCR), and DMA operation register (DMAOR), the DMAC transfers data
according to the following procedure:
1. Checks that transfer is enabled (DE = 1, DME = 1, AE = 0, TE = 0, NMIF = 0)
2. When transfer is enabled and a transfer request is generated, the DMAC transfers 1 transfer
unit of data (set with the TS0 and TS1 bits). In auto request mode, the transfer operation begins
automatically when the DE bit and DME bit are set to 1. The DMATCR value will be
decremented on each transfer. The actual transfer flows vary according to the address mode
and bus mode.
3. When the specified number of transfers have been completed (when DMATCR reaches 0), the
transfer operation ends normally. If the IE bit in CHCR is set to 1 at this time, a DEI interrupt
is sent to the CPU.
4. When an NMI interrupt is generated, the transfer operation is aborted. The transfer operation is
also aborted when the DE bit in CHCR or the DME bit in DMAOR is changed to 0.
Figure 14.2 shows a flowchart of this procedure.
Rev. 5.00 Dec 12, 2005 page 398 of 1034
REJ09B0254-0500