SH7727 Datasheet, PDF (350/1109 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperH RISC engine Family/SH7700 Series

Section 10 On-Chip Oscillation Circuits
Decoupling Capacitors: Insert a laminated ceramic capacitor of 0.01 to 0.1 µF as a passive
capacitor for each V_SS/V_CC pair. Mount the passive capacitors to the SH3 power supply pins, and
use components with a frequency characteristic suitable for the SH3 operating frequency, as well
as a suitable capacitance value.
Digital system V_SS/V_CC pairs: 35-37, 91-93, 137-139, 155-157, 177-178, 200-202
Digital system V_SS Q/V_CC Q pairs: 18-20, 29-31, 42-44, 53-55, 64-66, 75-77, 86-88, 100-102, 115-
117, 132-134, 159-161, 188-190, 207-209
On-chip oscillator V_SS/V_CC pairs: 1-4
When Using a PLL Oscillator Circuit: Keep the wiring from the PLL V_CC and V_SS connection
pattern to the power supply pins short, and make the pattern width large, to minimize the
inductance component. Ground the oscillation stabilization capacitors C1 and C2 to V_SS (PLL1)
and V_SS (PLL2), respectively. Place C1 and C2 close to the CAP1 and CAP2 pins and do not
locate a wiring pattern in the vicinity. In clock mode 7, connect the EXTAL pin to V_CC or V_SS and
leave the XTAL pin open.
Avoid crossing
signal lines
V_CC (PLL2)
CAP2
C2
V_SS (PLL2)
V_CC (PLL1)
CAP1
C1
V_SS (PLL1)
Power supply
V_CC
Reference values
C1 = 470 pF
C2 = 470 pF
V_SS
Figure 10.5 Points for Attention when Using PLL Oscillator Circuit
Notes on using pins CKIO and CKIO2 as the clock outputs: Perform board design so that the
sum of pin capacitances of the CPU and socket that are connected to pins are 50 pF or less.
Rev. 5.00 Dec 12, 2005 page 278 of 1034
REJ09B0254-0500