SH7727 Datasheet, PDF (396/1109 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperH RISC engine Family/SH7700 Series

Section 12 Bus State Controller (BSC)
For ordinary memory and burst ROM, byte, word, or longword can be selected as the bus width
using the A5SZ1 to A5SZ0 bits of BCR2. For the PCMCIA interface, byte, and word can be
selected as the bus width using the A5SZ1 to A5SZ0 bits of BCR2.
When the area 5 space is accessed and ordinary memory is connected, a CS5 signal is asserted. An
RD signal that can be used as OE and the WE0 to WE3 signals for write control are also asserted.
When the PCMCIA interface is used, the CE1A signal, CE2A signal, RD signal as OE signal, and
WE, ICIORD, ICIOWR signal are asserted.
The number of bus cycles is selected between 0 and 10 wait cycles using the A5W2 to A5W0 bits
of WCR2. With the PCMCIA interface, from 0 to 38 wait cycles can be selected using the A5W2
to A5W0 bits of WCR2 and the A5W3 bit of PCR. In addition, any number of waits can be
inserted in each bus cycle by means of the external wait pin (WAIT).
When a burst function is used, the bus cycle pitch of the burst cycle is determined within a range
of 2 to 11 (2 to 39 for the PCMCIA interface) according to the number of waits. The setup and
hold times of address/CS5 for the read/write strobe signal can be set in the range 0.5 to 7.5 cycles
using A5TED2 to A5TED0 and A5TEH2 to A5TEH0 bits of the PCR register. (Single-cycle units)
Area 6: Area 6 physical addresses A28 to A26 are 110. Address A31 to A29 are ignored and the
address range is the 64 Mbytes at H'18000000 + H'20000000 × n to H'1BFFFFFF + H'20000000 ×
n (n = 0 to 6 and n = 1 to 6 are the shadow spaces).
Ordinary memories like SRAM and ROM as well as burst ROM and PCMCIA interfaces can be
connected to this space. When the PCMCIA interface is used, the IC memory card interface
address range is 32 Mbytes at H'18000000 + H'20000000 × n to H'19FFFFFF + H'2000'000 × n
and 'he I/O card interface address range is 32 Mbytes at H'1A000000 + H'20000000 × n to
H'1BFFFFFF + H'20000000 × n (n = 0 to 6 and n = 1 to 6 are the shadow spaces).
For ordinary memory and burst ROM, byte, word, or longword can be selected as the bus width
using the A6SZ1 to A6SZ0 bits of BCR2. For the PCMCIA interface, byte, and word can be
selected as the bus width using the A6SZ1 to A6SZ0 bits of BCR2.
When the area 6 space is accessed and ordinary memory is connected, a CS6 signal is asserted. An
RD signal that can be used as OE and the WE0 to WE3 signals for write control are also asserted.
When the PCMCIA interface is used, the CI1B signal, CE2B signal, RD signal as OE signal, and
WE, ICIORD, and ICIOWR signals are asserted.
The number of bus cycles is selected between 0 to 10 wait cycles using the A6W2 to A6W0 bits of
WCR2. With the PCMCIA interface, from 0 to 38 wait cycles can be selected using the A6W2 to
A6W0 bits of WCR2 and the A6W3 bit of PCR. In addition, any number of waits can be inserted
in each bus cycle by means of the external wait pin (WAIT). The bus cycle pitch of the burst cycle
Rev. 5.00 Dec 12, 2005 page 324 of 1034
REJ09B0254-0500