SH7727 Datasheet, PDF (458/1109 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperH RISC engine Family/SH7700 Series

Section 14 Direct Memory Access Controller (DMAC)
14.2.3 DMA Transfer Count Registers 0 to 3 (DMATCR0 to DMATCR3)
Bit: 31
30
29
28
27
26
25
24
Initial value: —
—
—
—
—
—
—
—
R/W: R
R
R
R
R
R
R
R
Bit: 23
22
21
20
...
0
...
Initial value: —
—
—
—
...
—
R/W: R/W
R/W
R/W
R/W
...
R/W
The DMA transfer count registers 0 to 3 (DMATCR0 to DMATCR3) are 24-bit read/write
registers that specify the DMA transfer count (bytes, words, or longwords). The number of
transfers is 1 when the setting is H'000001, and 16777216 (the maximum) when H'000000 is set.
During a DMA transfer, these registers indicate the remaining transfer count.
To transfer data in 16 bytes, one 16-byte transfer (128 bits) counts one.
The upper eight bits in DMATCR are always read as 0 and should only be written with 0.
Initial values are undefined after a reset. The previous value is held in standby mode.
Rev. 5.00 Dec 12, 2005 page 386 of 1034
REJ09B0254-0500