SH7727 Datasheet, PDF (849/1109 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperH RISC engine Family/SH7700 Series

Section 25 LCD Controller
25.2.8 LCDC Palette Control Register (LDPALCR)
LDPALCR selects whether the CPU or LCDC accesses the palette memory. When the palette
memory is being used for display operation, display mode should be selected. When the palette
memory is being written to, CPU access mode should be selected.
Bit: 15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
—
—
—
—
—
—
—
—
—
—
— PALS —
—
— PALEN
Initial value: ₀
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
R/W: _R
R
R
R
R
R
R
R
R
R
R
R
R
R
R R/W
Bits 15 to 5 and 3 to 1—Reserved
Bit 4—Palette State (PALS): Indicates the access right state of the palette.
Bit 4
PALS
0
1
Description
Display mode: LCDC uses the palette
CPU access mode: The host (CPU) uses the palette
(Initial value)
Bit 0—Palette Read/Write Enable (PALEN): Controls CPU accesses to the palette.
Bit 0
PALEN
0
1
Description
Display mode: LCDC uses the palette
CPU access mode: The host (CPU) uses the palette
(Initial value)
Rev. 5.00 Dec 12, 2005 page 777 of 1034
REJ09B0254-0500