SH7727 Datasheet, PDF (446/1109 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperH RISC engine Family/SH7700 Series

Section 13 Li Bus State Controller (LBSC)
Bits 13 and 12—RAS–CAS Delay (RCD1, RCD0): When synchronous DRAM interface is
selected, these bits set the bank active read/write command delay time.
Bit 13: RCD1
0
1
Bit 12: RCD0
0
1
0
1
Description
1 cycle
2 cycles
3 cycles
4 cycles
(Initial value)
Bits 11 and 10—Write-Precharge Delay (TRWL1, TRWL0): The TRWL bits set the
synchronous DRAM write-precharge delay time. This designates the time between the end of a
write cycle and the automatic precharge activation. After the write cycle, the next bank-active
command is not issued for the period TPC + TRWL.
Bit 11: TRWL1
0
1
Bit 10: TRWL0
0
1
0
1
Description
1 cycle
2 cycles
3 cycles
Reserved (Setting disabled)
(Initial value)
Bits 9 and 8—CAS-Before-RAS Refresh RAS Assert Time (TRAS1, TRAS0): When
synchronous DRAM interface is selected, no bank-active command is issues during the period
TPC + TRAS after an auto-refresh command.
Bit 9: TRAS1
0
1
Bit 8: TRAS0
0
1
0
1
Description
2 cycles
3 cycles
4 cycles
5 cycles
(Initial value)
Bit 7—Reserved: This bit is always read as 0 and should only be written with 0.
Rev. 5.00 Dec 12, 2005 page 374 of 1034
REJ09B0254-0500