SH7727 Datasheet, PDF (292/1109 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperH RISC engine Family/SH7700 Series

Section 8 User Break Controller
Bits 27 to 0—Branch Source Address (BSA27 to BSA0): These bits store the last fetched
address before branch.
8.2.12 Branch Destination Register (BRDR)
Bit: 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
DVF — — — BDA BDA BDA BDA BDA BDA BDA BDA BDA BDA BDA BDA
27 26 25 24 23 22 21 20 19 18 17 16
Initial value: 0
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
R/W: R R R R R R R R R R R R R R R R
Bit: 15 14 13 12 11 10 9
8
7
6
5
4
3
2
1
0
BDA BDA BDA BDA BDA BDA BDA BDA BDA BDA BDA BDA BDA BDA BDA BDA
15 14 13 12 11 10 9
8
7
6
5
4
3
2
1
0
Initial value: *
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
R/W: R R R R R R R R R R R R R R R R
Note: * Undefined
BRDR is a 32-bit read register. BRDR stores the branch destination fetch address. BRDR has the
flag bit that is set to 1 when branch occurs. This flag bit is cleared to 0, when BRDR is read and
also initialized by power-on resets or manual resets. Other bits are not initialized by resets. Eight
BRDR registers have queue structure and a stored register is shifted every branch.
Bit 31—BRDR Valid Flag (DVF): Indicates whether a branch destination address is stored.
When a branch destination address is fetched, this flag is set to 1. This flag is cleared to 0 in
reading BRDR.
Bit 31: DVF
0
1
Description
The value of BRDR register is invalid
The value of BRDR register is valid
Bits 30 to 28—Reserved: These bits are always read as 0. The write value should always be 0.
Bits 27 to 0—Branch Destination Address (BDA27 to BDA0): These bits store the first fetched
address after branch.
Rev. 5.00 Dec 12, 2005 page 220 of 1034
REJ09B0254-0500