SH7727 Datasheet, PDF (699/1109 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperH RISC engine Family/SH7700 Series

Section 20 Serial IO (SIOF)
20.2.11 Receive Data Register (SIRDR)
This register reads receive data of SIOF. The data from receive FIFO is stored in this register. This
register is initialized at power on reset, software reset, or transmit reset.
Bit: 31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
SIRDL SIRDL SIRDL SIRDL SIRDL SIRDL SIRDL SIRDL SIRDL SIRDL SIRDL SIRDL SIRDL SIRDL SIRDL SIRDL
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Initial value: 0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
R/W: R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
Bit: 15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
SIRDR SIRDR SIRDR SIRDR SIRDR SIRDR SIRDR SIRDR SIRDR SIRDR SIRDR SIRDR SIRDR SIRDR SIRDR SIRDR
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Initial value: 0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
R/W: R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
Bits 31 to 16—Receive Data for Left Channel (SIRDL15 to SIRDL0): These bits stores
received data from RXD_SIO as left channel data. The position of left channel side data are
assumed as the position what defined by RDLA bit of SIRDAR register.
These bits are effective when 1 is written to RDLE bit of SIRDAR register.
Bits 15 to 0—Receive Data for Right Channel (SIRDR15 to SIRDR0): These bits stores
received data from RXD_SIO as right channel data. The position of left channel side data are
assumed as the position what defined by RDRA bit of SIRDAR register.
These bits are effective when 1 is written to RDRE bit of SIRDAR register.
Rev. 5.00 Dec 12, 2005 page 627 of 1034
REJ09B0254-0500