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SH7727 Datasheet, PDF (835/1109 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperH RISC engine Family/SH7700 Series
Section 25 LCD Controller
Section 25 LCD Controller
25.1 Overview
A unified memory architecture is adopted for the LCD controller (LCDC) so that the image data
for display is stored in system memory. The LCDC module reads data from system memory, uses
the pallet memory to determine the colors, then puts the display on the LCD panel. It is possible to
connect the LCDC to the LCD module of most types other than microcomputer bus interface types
and NTSC/PAL types and those that apply the LVDS interface∗.
Note: * An LVDS-conversion LSI can be connected to the LCDC to allow connection to an
LVDS interface.
25.1.1 Features
The LCDC has the following features.
• Panel interface
 Serial interface method
 Supports data formats for STN/dual-STN/TFT panels (8/12/16/18-bit bus width)
• Supports 4/8/15/16-bpp (bit per pixel) color modes
• Supports 1/2/4/6-bpp grayscale modes
• Supports LCD-panel sizes from 16 × 1 to 1024 × 1024
• 24-bit color palette memory (16 of the 24 bits are valid; R:5/G:6/B:5)
• STN/DSTN panels are prone to flicker and shadowing. The controller applies 65536-color
control by 24-bit space-modulation FRC with 8-bit RGB values for reduced flicker.
• Dedicated display memory is unnecessary because the controller uses synchronous DRAM
which is connected to area 3 of the CPU’s memory map
• The display is stable because of the large 2.4-kbyte line buffer
• Supports the inversion of the output signal to suit the LCD panel’s signal polarity
• Supports variation of the burst length in reading from the synchronous DRAM, to realize high-
speeds in the reading of data
• Supports the selection of data formats (the endian setting for bytes, backed pixel method) by
register settings
• A hardware-rotation mode is included to support the use of landscape-format LCD panels as
portrait-format LCD panels (the horizontal width of the panel before rotation must be within
320 pixels—see table 25.3).
Rev. 5.00 Dec 12, 2005 page 763 of 1034
REJ09B0254-0500