SH7727 Datasheet, PDF (66/1109 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperH RISC engine Family/SH7700 Series

Table 2.34 Examples of NOPX and NOPY Instruction Codes ................................................ 96
Section 3 Memory Management Unit (MMU)
Table 3.1 Register Configuration ........................................................................................... 103
Table 3.2 Access States Designated by D, C, and PR Bits..................................................... 110
Section 4 Exception Handling
Table 4.1 Register Configuration ........................................................................................... 131
Table 4.2 Exception Event Vectors ........................................................................................ 133
Table 4.3 Exception Codes..................................................................................................... 136
Table 4.4 Types of Reset........................................................................................................ 141
Section 5 Cache
Table 5.1 Cache Specifications .............................................................................................. 149
Table 5.2 LRU and Way Replacement................................................................................... 151
Table 5.3 Register Configuration ........................................................................................... 151
Table 5.4 LRU and Way Replacement (when W2LOCK=1)................................................. 153
Table 5.5 LRU and Way Replacement (when W3LOCK=1)................................................. 153
Table 5.6 LRU and Way Replacement (when W2LOCK=1 and W3LOCK=1) .................... 154
Section 6 X/Y Memory
Table 6.1 X/Y Memory Specifications................................................................................... 161
Section 7 Interrupt Controller (INTC)
Table 7.1 Pin Configuration ................................................................................................... 167
Table 7.2 Register Configuration ........................................................................................... 168
Table 7.3 IRL3 to IRL0 Pins and Interrupt Levels................................................................. 171
Table 7.4 Interrupt Exception Handling Sources and Priority (IRQ Mode)........................... 174
Table 7.5 Interrupt Exception Handling Sources and Priority (IRL Mode) ........................... 176
Table 7.6 Interrupt Level and INTEVT Code ........................................................................ 178
Table 7.7 Interrupt Request Sources and IPRA to IPRG........................................................ 179
Table 7.8 Interrupt Response Time ........................................................................................ 200
Section 8 User Break Controller
Table 8.1 Register Configuration ........................................................................................... 205
Table 8.2 Data Access Cycle Addresses and Operand Size Comparison Conditions ............ 223
Section 9 Power-Down Modes and Software Reset
Table 9.1 Power-Down Modes............................................................................................... 234
Table 9.2 Pin Configuration ................................................................................................... 235
Table 9.3 Register Configuration ........................................................................................... 235
Rev. 5.00 Dec 12, 2005 page lxvi of lxxii