SH7727 Datasheet, PDF (946/1109 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperH RISC engine Family/SH7700 Series

Section 28 A/D Converter
Table 28.4 A/D Conversion Time (Single Mode)
CKS = 0
Symbol Min
Typ Max
Min
A/D conversion start
tD
delay
17
—
28
10
Input sampling time
tSPL
—
129 —
—
A/D conversion time
tCONV
514
—
525
259
Note: Values in the table are numbers of states (tcyc).
CKS = 1
Typ
Max
—
17
65
—
—
266
28.4.5 External Trigger Input Timing
A/D conversion can be externally triggered. When the TRGE1, TRGE0 bits are set to 1 in ADCR,
external trigger input is enabled at the ADTRG pin. A high-to-low transition at the ADTRG pin
sets the ADST bit to 1 in ADCSR, starting A/D conversion. Other operations, regardless of the
conversion mode, are the same as if the ADST bit had been set to 1 by software. Figure 28.7
shows the timing.
Pφ
ADTRG
External
trigger signal
ADST
A/D conversion
Figure 28.7 External Trigger Input Timing
Rev. 5.00 Dec 12, 2005 page 874 of 1034
REJ09B0254-0500