SH7727 Datasheet, PDF (770/1109 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperH RISC engine Family/SH7700 Series

Section 23 USB Function Controller
23.5.9 USB Trigger Register (USBTRG)
USBTRG generates one-shot triggers to control the transmit/receive sequence for each endpoint.
Bit:
7
6
5
4
3
2
1
0
—
EP3
EP1
EP2
—
EP0s EP0o EP0i
PKTE RDFN PKTE
RDFN RDFN PKTE
R/W: W
W
W
W
W
W
W
W
Bit 7—Reserved
Bit 6—EP3 Packet Enable (EP3 PKTE): After one packet of data has been written to the
endpoint 3 transmit FIFO buffer, the transmit data is fixed by writing 1 to this bit.
Bit 5—EP1 Read Complete (EP1 RDFN): Write 1 to this bit after one packet of data has been
read from the endpoint 1 FIFO buffer. The endpoint 1 receive FIFO buffer has a dual-FIFO
configuration. Writing 1 to this bit initializes the FIFO that was read, enabling the next packet to
be received.
Bit 4—Endpoint 2 Packet Enable (EP2 PKTE): After one packet of data has been written to the
endpoint 2 FIFO buffer, the transmit data is fixed by writing 1 to this bit.
Bit 3—Reserved
Bit 2—EP0s Read Complete (EP0s RDFN): Write 1 to this bit after EP0s command FIFO data
has been read. Writing 1 to this bit enables transmission/reception of data in the following data
stage. A NACK handshake is returned in response to transmit/receive requests from the host in the
data stage until 1 is written to this bit.
Bit 1—EP0o Read Complete (EP0o RDFN): Writing 1 to this bit after one packet of data has
been read from the endpoint 0 transmit FIFO buffer initializes the FIFO buffer, enabling the next
packet to be received.
Bit 0—EP0i Packet Enable (EP0i PKTE): After one packet of data has been written to the
endpoint 0 transmit FIFO buffer, the transmit data is fixed by writing 1 to this bit.
Rev. 5.00 Dec 12, 2005 page 698 of 1034
REJ09B0254-0500