SH7727 Datasheet, PDF (862/1109 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperH RISC engine Family/SH7700 Series

Section 25 LCD Controller
25.3 Operation
25.3.1 LCD Module Sizes which can be Displayed in this LCDC
This LCDC is capable of controlling displays with up to 1024 × 1024 dots and 16 bpp (bits per
pixel). The image data for display is stored in system memory, which is shared with the CPU.
This LCDC should read the data from system memory between display periods.
The SH7727 has a maximum 32-burst memory read operation and a 2.4-kbyte line buffer, so
although a complete breakdown of the display is unlikely, there may be some problems with the
display depending on the combination.
The bus-occupancy rate described below should not, as a rule, exceed 40%.
Overhead coefficient × total number of display pixels ((HDCN + 1) × 8 × (VDLN + 1)) ×
Bus-occupancy rate (%) =
frame rate (Hz) × number of colors (bpp) × 100
CKIO (Hz) × bus width (bits)
The overhead coefficient depends on the bus used by the SDRAM in CL2, as indicated below.
If the hardware rotation function is not used (ROT = 0), the overhead coefficient is 1.375 if a 32-
bit bus is used and 1.188 if a 16-bit bus is used.
If the hardware rotation function is used (ROT = 1), the overhead coefficient is determined by the
access unit select (AU) setting and the bus width, as follows.
Access Unit Select (AU) Setting
4-burst operation
8-burst operation
16-burst operation
32-burst operation
32-Bit Bus
2.500
1.750
1.375
1.188
16-Bit Bus
1.750
1.375
1.188
1.094
Rev. 5.00 Dec 12, 2005 page 790 of 1034
REJ09B0254-0500