SH7727 Datasheet, PDF (771/1109 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperH RISC engine Family/SH7700 Series

Section 23 USB Function Controller
23.5.10 USBFIFO Clear Register (USBFCLR)
USBFCLR is provided to initialize the FIFO buffers for each endpoint. Writing 1 to a bit clears all
the data in the corresponding FIFO buffer. The corresponding interrupt flag is not cleared. Do not
clear a FIFO buffer during transmission/reception.
Bit:
7
6
5
4
3
—
EP3
EP1
EP2
—
CLR
CLR
CLR
R/W: W
W
W
W
W
2
1
0
—
EP0o EP0i
CLR
CLR
W
W
W
Bit 7—Reserved
Bit 6—EP3 Clear (EP3 CLR): When 1 is written to this bit, the endpoint 3 transmit FIFO buffer
is initialized.
Bit 5—EP1 Clear (EP1 CLR): When 1 is written to this bit, both FIFOs in the endpoint 1 receive
FIFO buffer are initialized.
Bit 4—EP2 Clear (EP2 CLR): When 1 is written to this bit, both FIFOs in the endpoint 2
transmit FIFO buffer are initialized.
Bits 3 and 2—Reserved
Bit 1—EP0o Clear (EP0o CLR): When 1 is written to this bit, the endpoint 0 receive FIFO
buffer is initialized.
Bit 0—EP0i Clear (EP0i CLR): When 1 is written to this bit, the endpoint 0 transmit FIFO
buffer is initialized.
23.5.11 USBEP0o Receive Data Size Register (USBEPSZ0O)
USBEPSZ0O indicates, in bytes, the amount of data received from the host by endpoint 0.
Rev. 5.00 Dec 12, 2005 page 699 of 1034
REJ09B0254-0500