SH7727 Datasheet, PDF (479/1109 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperH RISC engine Family/SH7700 Series

CKIO
A25 to A0
CSn
D31 to D0
RD
WEn
DACKn
Section 14 Direct Memory Access Controller (DMAC)
Transfer source
address
Transfer destination
address
Data read cycle
Data write cycle
(1st cycle)
(2nd cycle)
Note: When DACK is output in a read cycle during transfer between external memories,
the output timing is the same as that of CSn.
Figure 14.6 Example of DMA Transfer Timing in the Direct Address Mode
(Transfer Source: Ordinary Memory, Transfer Destination: Ordinary Memory)
Rev. 5.00 Dec 12, 2005 page 407 of 1034
REJ09B0254-0500