SH7727 Datasheet, PDF (56/1109 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperH RISC engine Family/SH7700 Series

Figure 12.27 Basic Timing for PCMCIA Memory Card Interface Burst Access ........................ 355
Figure 12.28 Wait Timing for PCMCIA Memory Card Interface Burst Access ......................... 356
Figure 12.29 PCMCIA Space Assignment .................................................................................. 357
Figure 12.30 Basic Timing for PCMCIA I/O Card Interface ...................................................... 359
Figure 12.31 Wait Timing for PCMCIA I/O Card Interface ....................................................... 360
Figure 12.32 Dynamic Bus Sizing Timing for PCMCIA I/O Card Interface .............................. 361
Figure 12.33 Waits between Access Cycles ................................................................................ 363
Figure 12.34 Pins A25 to A0 Pull-Up Timing............................................................................. 364
Figure 12.35 Pins D31 to D0 Pull-Up Timing (Read Cycle)....................................................... 364
Figure 12.36 Pins D31 to D0 Pull-Up Timing (Write Cycle) ...................................................... 365
Section 13 Li Bus State Controller (LBSC)
Figure 13.1 Block Diagram of Li Bus Architecture................................................................... 377
Section 14 Direct Memory Access Controller (DMAC)
Figure 14.1 DMAC Block Diagram .......................................................................................... 381
Figure 14.2 DMAC Transfer Flowchart .................................................................................... 399
Figure 14.3 Operation in Round-Robin Mode........................................................................... 403
Figure 14.4 Channel Priority Order in Round-Robin Mode ...................................................... 404
Figure 14.5 Operation in Direct Address Mode......................................................................... 406
Figure 14.6 Example of DMA Transfer Timing in the Direct Address Mode
(Transfer Source: Ordinary Memory, Transfer Destination: Ordinary Memory)... 407
Figure 14.7 Example of DMA Transfer Timing in the Direct Address Mode
(16-byte Transfer, Transfer Source: Ordinary Memory, Transfer Destination:
Ordinary Memory) ................................................................................................. 408
Figure 14.8 Example of DMA Transfer Timing in the Direct Address Mode
(16-byte Transfer, Transfer Source: Synchronous DRAM, Transfer Destination:
Ordinary Memory) ................................................................................................. 408
Figure 14.9 Operation in Indirect Address Mode (When the External Memory Space
is Set to 16-bit Width) ............................................................................................ 410
Figure 14.10 Example of Transfer Timing in Indirect Address Mode
(Transfer between External Memories, External Memory with 16-bit Width) ...... 411
Figure 14.11 Data Flow in Single Address Mode........................................................................ 412
Figure 14.12 Example of DMA Transfer Timing in Single Address Mode ................................ 413
Figure 14.13 Example of DMA Transfer Timing in Single Address Mode
(External Memory Space (Ordinary Memory) → External Device with DACK) .. 414
Figure 14.14 Transfer Example in Cycle-Steal Mode ................................................................. 415
Figure 14.15 Example of Transfer in Burst Mode....................................................................... 415
Figure 14.16 Bus State in Multiple Channel Operation............................................................... 417
Figure 14.17 Cycle-Steal Mode, Level Input (CPU Access: 2 Cycles) ....................................... 420
Figure 14.18 Cycle-Steal Mode, Level Input (CPU Access: 3 Cycles) ....................................... 421
Rev. 5.00 Dec 12, 2005 page lvi of lxxii