SH7727 Datasheet, PDF (590/1109 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperH RISC engine Family/SH7700 Series

Section 17 Serial Communication Interface (SCI)
Serial Data Reception (Asynchronous Mode):
Figure 17.10 shows a sample flow chart for serial data reception. After enabling the SCI reception,
receive serial data following the procedure shown below:
Start reception
(1) Receive error processing and
break detection:
Read ORER, PER, and FER
bits in SCSSR
If a receive error occurs, read
the ORER, PER and FER bits
of the SCSSR to identify the
error. After executing the
Yes
PER, FER, ORER = 1?
necessary error processing,
clear ORER, PER and FER all
to 0. Receiving cannot resume if
No
(1)
ORER, PER or FER remain set
to 1. When a framing error
Error processing _{occurs, the RxD pin can be read}
to detect the break state.
Read the RDRF bit in SCSSR (2)
No
RDRF = 1?
Yes
Read reception data of SCRDR
and clear RDRF bit in SCSSR to 0 ⁽³⁾
(2) SCI status check and receive-
data read:
Read the serial status register
(SCSSR), check that RDRF is
set to 1, then read receive data
from the receive data register
(SCRDR) and clear RDRF to 0.
The RXI interrupt can also be
used to determine if the RDRF
bit has changed from 0 to 1.
No
All data received?
Yes
Clear the RE bit in SCSCR to 0
(3) To continue receiving serial
data:
Read the SCRDR receive data
and clear the RDRF flag in
SCSSR to 0 before the stop bit
of the current frame is received.
End reception
Figure 17.10 Sample Serial Reception Data Flowchart (1)
Rev. 5.00 Dec 12, 2005 page 518 of 1034
REJ09B0254-0500