SH7727 Datasheet, PDF (610/1109 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperH RISC engine Family/SH7700 Series

Section 17 Serial Communication Interface (SCI)
17.4 SCI Interrupt Sources
The SCI has four interrupt sources in each channel: Transmit-end (TEI), receive-error (ERI),
receive-data-full (RXI), and transmit-data-empty (TXI). Table 17.13 lists the interrupt sources and
indicates their priority. These interrupts can be enabled and disabled by the TIE, RIE, and TEIE
bits in the serial control register (SCSCR). Each interrupt request is sent separately to the interrupt
controller.
TXI is requested when the TDRE bit in the SCSSR is set to 1.
RXI is requested when the RDRF bit in the SCSSR is set to 1.
ERI is requested when the ORER, PER, or FER bit in the SCSSR is set to 1.
TEI is requested when the TEND bit in the SCSSR is set to 1. Where the TXI interrupt indicates
that transmit data writing is enabled, the TEI interrupt indicates that the transmit operation is
complete.
Table 17.13 SCI Interrupt Sources
Interrupt Source
ERI
RXI
TXI
TEI
Description
Receive error (ORER, PER, or FER)
Receive data full (RDRF)
Transmit data empty (TDRE)
Transmit end (TEND)
Priority When Reset Is Cleared
High
Low
See section 4, Exception Handling, for information on the priority order and relationship to non-
SCI interrupts.
Rev. 5.00 Dec 12, 2005 page 538 of 1034
REJ09B0254-0500