SH7727 Datasheet, PDF (418/1109 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperH RISC engine Family/SH7700 Series

Section 12 Bus State Controller (BSC)
performed after auto-refresh setting, but a way of carrying this out more dependably is to set a
short refresh request generation interval just while these dummy cycles are being executed. With
simple read or write access, the address counter in the synchronous DRAM used for auto-
refreshing is not initialized, and so the cycle must always be an auto-refresh cycle.
CKIO, CKIO2
A15 to A13
or A15 to A12
A11
TRp1 TRp2 TRp3 TRp4 TMw1 TMw2 TMw3 TMw4
A12 or A10
A9 to A2
CSn
RD/WR
RAS3
CAS
D31 to D0
CKE
(High)
Figure 12.21 Synchronous DRAM Mode Write Timing
Rev. 5.00 Dec 12, 2005 page 346 of 1034
REJ09B0254-0500