SH7727 Datasheet, PDF (501/1109 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperH RISC engine Family/SH7700 Series

Section 14 Direct Memory Access Controller (DMAC)
14.3.7 DMA Transfer Ending
DMA transfer ending conditions to terminate transfer differ according to the ending types,
individual channel ending and all channel ending. At a transfer end, the following conditions are
applied except the case when the DMA transfer count register (DMATCR) value reaches 0.
(a) Cycle-steal mode (external request, internal request, and auto request)
When a transfer ending condition is satisfied, DMAC transfer request acceptance is suspended.
The DMAC stops operation after completing the number of transfers that has accepted before
the ending conditions are satisfied.
In the cycle-steal mode, the same operation is provided regardless of the transfer request
detection method; the level detection or the edge detection.
(b) Burst mode, edge detection (external request, internal request, and auto request)
The timing of DMAC operation ending after an ending condition is satisfied differs from that
in cycle steal mode. In the edge detection in the burst mode, though only one transfer request
is generated at the DMAC start-up, a stop request sampling is performed in the same timing as
a transfer request sampling in the cycle-steal mode. As a result, the period when a stop request
is not sampled is regarded as the period when a transfer request is generated, and after
performing the DMA transfer for this period, the DMAC stops operation.
(c) Burst mode, level detection (external request)
Same as described in (a).
(d) Bus timing when transfers are suspended
Transfer is suspended when one transfer ends. Even if a transfer ending condition is satisfied
during a read with the direct address transfer in the dual address mode, the subsequent write
process is executed, and after the transfer in (a) to (c) above has been executed, DMAC
operation suspends.
Rev. 5.00 Dec 12, 2005 page 429 of 1034
REJ09B0254-0500