SH7727 Datasheet, PDF (973/1109 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperH RISC engine Family/SH7700 Series

Section 30 PC Card Controller (PCC)
Bits 6 and 5—PCC0IREQ Request Enable (IREQE1, IREQE0): These bits enable or disable
IREQ pin interrupt requests and select the interrupt mode when the PC card connected to area 6 is
the I/O card interface type. Note that bit 5 (P0IREQ) in the area 6 card status change register
(PCC0CSCR) is cleared if the values in bits 6 and 5 in this register are changed. These bits have
no meaning on the IC memory card interface.
Bit 6:
IREQE1
0
0
1
1
Bit 5:
IREQE0
0
1
0
1
Description
IREQ requests are not accepted for the PC card connected to area 6. Bit
5 in the status change register (PCC0CSCR) functions as a read-only bit
that indicates the inverse of the IREQ pin signal.
(Initial value)
The level-mode IREQ interrupt request signal is accepted for the PC card
connected to area 6. In level mode, an interrupt occurs when level 0 of
the signal input from the IREQ pin is detected.
The pulse-mode IREQ interrupt request signal is accepted for the PC
card connected to area 6. In pulse mode, an interrupt occurs when a
falling edge from 1 to 0 of the signal input from the IREQ pin is detected.
The pulse-mode IREQ interrupt request signal is accepted for the PC
card connected to area 6. In pulse mode, an interrupt occurs when a
rising edge from 0 to 1 of the signal input from the IREQ pin is detected.
Bit 4—PCC0 Status Change Enable (P0SCE): When the PC card connected to area 6 is on the
I/O card interface, bit 4 enables or disables the interrupt request when the value of the BVD1 pin
(STSCHG pin) is changed. This bit has no meaning in the IC memory card interface.
Bit 4: P0SCE
0
1
Description
No interrupt occurs for the PC card connected to area 6 regardless of the
value of the BVD1 pin (STSCHG pin)
(Initial value)
An interrupt occurs for the PC card connected to area 6 when the value of
the BVD1 pin (STSCHG pin) is changed from 1 to 0
Bit 3—PCC0 Card Detect Change Enable (P0CDE): Bit 3 enables or disables the interrupt
request when the values of the CD1 and CD2 pins are changed.
Bit 3: P0CDE
0
1
Description
No interrupt occurs for the PC card connected to area 6 regardless of the
values of the CD1 and CD2 pins
(Initial value)
An interrupt occurs for the PC card connected to area 6 when the values of
the CD1 and CD2 pins are changed
Rev. 5.00 Dec 12, 2005 page 901 of 1034
REJ09B0254-0500