SH7727 Datasheet, PDF (847/1109 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperH RISC engine Family/SH7700 Series

Section 25 LCD Controller
25.2.6 LCDC Start Address Register for Lower Display Data Fetch (LDSARL)
LDSARL sets the start address from which data is fetched by the LCDC for lower display of the
LCD panel. When a DSTN panel is used, this register specifies the fetch start address for the lower
side of the panel.
Bit: 31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
—
—
—
—
—
— SAL25 SAL24 SAL23 SAL22 SAL21 SAL20 SAL19 SAL18 SAL17 SAL16
Initial value: 0
0
0
0
1
1
0
0
0
0
0
0
0
0
0
0
R/W: R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W
Bit: 15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
SAL15 SAL14 SAL13 SAL12 SAL11 SAL10 SAL9 SAL8 SAL7 SAL6 SAL5 SAL4 SAL3 SAL2 SAL1 SAL0
Initial value: 0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
R/W: R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W
Bits 31 to 26—Reserved
Bits 25 to 0—Start Address for Lower Panel Display Data Fetch (SAL31 to SAL0): The start
address for data fetch of the display data must be set within the synchronous DRAM area of area
3.
STN and TFT: Cannot be used
DSTN: Start address for fetching display data corresponding to the lower panel
Note:
The minimum alignment unit of LDSARU and LDSARL is four bytes. Because the LCDC
handles these values as longword data, the values written to the lower two bits of each
register are always treated as 0. The lower two bits of each register are always read as 0.
For 1 or 2 bpp, set the registers so that the start of each line is aligned with the longword
boundary (32 bits). (Data at the start of each line is always valid.) Data that exceeds the
longword boundary at the end of each line (1, 2, or 3 bytes) will be discarded. For 4, 8, 15,
16, or 32 bpp, set the registers so that the start of each line is aligned with the longword
boundary (32 bits).
Rev. 5.00 Dec 12, 2005 page 775 of 1034
REJ09B0254-0500