AC82G41SLGQ3 Datasheet, PDF (99/604 Pages) Intel Corporation – Intel® 4 Series Chipset Family

DRAM Controller Registers (D0:F0)
5.1.16 PCIEXBAR—PCI Express Register Range Base Address
B/D/F/Type:
Address Offset:
Default Value:
Access:
Size:
0/0/0/PCI
60-67h
00000000E0000000h
RO, R/W/L, R/W/L/K
64 bits
This is the base address for the PCI Express configuration space. This window of
addresses contains the 4 KB of configuration space for each PCI Express device that
can potentially be part of the PCI Express Hierarchy associated with the (G)MCH. There
is not actual physical memory within this window of up to 256 MB that can be
addressed. The actual length is determined by a field in this register. Each PCI Express
Hierarchy requires a PCI Express BASE register. The (G)MCH supports one PCI Express
hierarchy. The region reserved by this register does not alias to any PCI 2.3 compliant
memory mapped space. For example MCHBAR reserves a 16 KB space and CHAPADR
reserves a 4 KB space both outside of PCIEXBAR space. They cannot be overlayed on
the space reserved by PCIEXBAR for devices 0 and 7 respectively.
On reset, this register is disabled and must be enabled by writing a 1 to the enable field
in this register. This base address shall be assigned on a boundary consistent with the
number of buses (defined by the Length field in this register), above TOLUD and still
within 64 bit addressable memory space. All other bits not decoded are read only 0.
The PCI Express Base Address cannot be less than the maximum address written to the
Top of physical memory register (TOLUD). Software must ensure that these ranges do
not overlap with known ranges located above TOLUD. Software must ensure that the
sum of Length of enhanced configuration region + TOLUD + (other known ranges
reserved above TOLUD) is not greater than the 64-bit addressable limit of 64 GB. In
general system implementation and number of PCI/PCI express/PCI-X buses supported
in the hierarchy will dictate the length of the region.
Note:
All the bits in this register are locked in Intel TXT mode (82Q45/82Q43 GMCH only).
Bit
63:36
35:28
Access
RO
R/W/L
Default
Value
0000000h
0Eh
RST/
PWR
Core
Core
Description
Reserved
PCI Express Base Address (PCIEXBAR): This field
corresponds to bits 35:28 of the base address for PCI
Express enhanced configuration space. BIOS will program
this register resulting in a base address for a contiguous
memory address space; size is defined by bits 2:1 of this
register.
This Base address shall be assigned on a boundary
consistent with the number of buses (defined by the Length
field in this register) above TOLUD and still within 64-bit
addressable memory space. The address bits decoded
depend on the length of the region defined by this register.
The address used to access the PCI Express configuration
space for a specific device can be determined as follows:
PCI Express Base Address + Bus Number * 1MB + Device
Number * 32KB + Function Number * 4KB
The address used to access the PCI Express configuration
space for Device 1 in this component is:
PCI Express Base Address + 0 * 1MB + 1 * 32KB + 0 *
4KB = PCI Express Base Address + 32KB.
Remember that this address is the beginning of the 4 KB
space that contains both the PCI compatible configuration
space and the PCI Express extended configuration space.
Datasheet
99