AC82G41SLGQ3 Datasheet, PDF (387/604 Pages) Intel Corporation – Intel® 4 Series Chipset Family

Intel^® Manageability Engine Subsystem Registers
10.9.1
ID—Identification
B/D/F/Type:
Address Offset:
Default Value:
Access:
Size:
0/3/3/PCI
0-3h
2E078086h
RO
32 bits
This register, combined with the Device Identification register, uniquely identifies any
PCI device.
Bit
31:16
15:0
Access
RO
RO
Default
Value
2E07h
8086h
RST/PWR
Description
Core
Core
Device ID (DID): Assigned by manufacturer, identifies
the device.
Vendor ID (VID): 16-bit field which indicates Intel is the
vendor, assigned by the PCI SIG.
10.9.2
CMD—Command Register
B/D/F/Type:
Address Offset:
Default Value:
Access:
Size:
0/3/3/PCI
4-5h
0000h
RO, R/W
16 bits
Reset: Host System reset or D3->D0 transition
This register provides basic control over the device's ability to respond to and perform
Host system related accesses.
Bit
15:11
Access
RO
10
R/W
9
RO
8
RO
7
RO
6
RO
5
RO
4
RO
3
RO
Default
Value
00h
0b
0b
0b
0b
0b
0b
0b
0b
RST/PWR
Description
Core
Core
Core
Core
Core
Core
Core
Core
Core
Reserved
Interrupt Disable (ID): This bit disables pin-based
INTx# interrupts. This bit has no effect on MSI operation.
1 = Internal INTx# messages will not be generated.
0 = Internal INTx# messages are generated if there is an
interrupt and MSI is not enabled.
Fast back-to-back enable (FBE): Reserved
SERR# Enable (SEE): The PT function never generates
an SERR#. Reserved
Wait Cycle Enable (WCC): Reserved
Parity Error Response Enable (PEE): No Parity
detection in PT functions. Reserved
VGA Palette Snooping Enable (VGA): Reserved
Memory Write and Invalidate Enable (MWIE):
Reserved
Special Cycle enable (SCE): Reserved
Datasheet
387