AC82G41SLGQ3 Datasheet, PDF (129/604 Pages) Intel Corporation – Intel® 4 Series Chipset Family

DRAM Controller Registers (D0:F0)
5.2.5
C0DRB3—Channel 0 DRAM Rank Boundary Address 3
B/D/F/Type:
Address Offset:
Default Value:
Access:
Size:
0/0/0/MCHBAR
206-207h
0000h
R/W, RO
16 bits
See the C0DRB0 register for detailed descriptions.
Bit
15:10
9:0
Access
RO
R/W
Default
Value
000000b
000h
RST/PWR
Description
Core
Core
Reserved
Channel 0 DRAM Rank Boundary Address 3
(C0DRBA3): This register defines the DRAM rank
boundary for rank3 of Channel 0 (64 MB granularity)
=(R3 + R2 + R1 + R0)
R0 = Total rank0 memory size/64MB
R1 = Total rank1 memory size/64MB
R2 = Total rank2 memory size/64MB
R3 = Total rank3 memory size/64MB
This register is locked by ME stolen Memory lock.
Datasheet
129