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AC82G41SLGQ3 Datasheet, PDF (12/604 Pages) Intel Corporation – Intel® 4 Series Chipset Family | |||
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10.7
10.8
10.9
10.6.11IDECLIRâIDE Cylinder Low In Register.................................................... 367
10.6.12IDCLOR1âIDE Cylinder Low Out Register Device 1.................................... 367
10.6.13IDCLOR0âIDE Cylinder Low Out Register Device 0.................................... 368
10.6.14IDCHOR0âIDE Cylinder High Out Register Device 0 .................................. 368
10.6.15IDCHOR1âIDE Cylinder High Out Register Device 1 .................................. 369
10.6.16IDECHIRâIDE Cylinder High In Register .................................................. 369
10.6.17IDEDHIRâIDE Drive/Head In Register ..................................................... 370
10.6.18IDDHOR1âIDE Drive Head Out Register Device 1 ..................................... 370
10.6.19IDDHOR0âIDE Drive Head Out Register Device 0 ..................................... 371
10.6.20IDESD0RâIDE Status Device 0 Register .................................................. 372
10.6.21IDESD1RâIDE Status Device 1 Register .................................................. 373
10.6.22IDECRâIDE Command Register .............................................................. 374
IDE BAR1 ....................................................................................................... 375
10.7.1 IDDCRâIDE Device Control Register ....................................................... 375
10.7.2 IDASRâIDE Alternate status Register ...................................................... 376
IDE BAR4 ....................................................................................................... 377
10.8.1 IDEPBMCRâIDE Primary Bus Master Command Register ............................ 378
10.8.2 IDEPBMDS0RâIDE Primary Bus Master Device Specific 0 Register ............... 378
10.8.3 IDEPBMSRâIDE Primary Bus Master Status Register ................................. 379
10.8.4 IDEPBMDS1RâIDE Primary Bus Master Device Specific 1 Register ............... 380
10.8.5 IDEPBMDTPR0âIDE Primary Bus Master Descriptor Table
Pointer Register Byte 0 .......................................................................... 380
10.8.6 IDEPBMDTPR1âIDE Primary Bus Master Descriptor Table
Pointer Register Byte 1 .......................................................................... 380
10.8.7 IDEPBMDTPR2âIDE Primary Bus Master Descriptor Table
Pointer Register Byte 2 .......................................................................... 381
10.8.8 IDEPBMDTPR3âIDE Primary Bus Master Descriptor Table
Pointer Register Byte 3 .......................................................................... 381
10.8.9 IDESBMCRâIDE Secondary Bus Master Command Register ........................ 382
10.8.10IDESBMDS0RâIDE Secondary Bus Master Device Specific 0 Register ........... 382
10.8.11IDESBMSRâIDE Secondary Bus Master Status Register ............................. 383
10.8.12IDESBMDS1RâIDE Secondary Bus Master Device Specific 1 Register ........... 383
10.8.13IDESBMDTPR0âIDE Secondary Bus Master Descriptor Table Pointer Register Byte
0 ........................................................................................................ 384
10.8.14IDESBMDTPR1âIDE Secondary Bus Master Descriptor Table Pointer Register Byte
1 ........................................................................................................ 384
10.8.15IDESBMDTPR2âIDE Secondary Bus Master Descriptor Table Pointer Register Byte
2 ........................................................................................................ 384
10.8.16IDESBMDTPR3âIDE Secondary Bus Master Descriptor Table Pointer Register Byte
3 ........................................................................................................ 385
Serial Port for Remote Keyboard and Text (KT) Redirection ................................... 386
10.9.1 IDâIdentification.................................................................................. 387
10.9.2 CMDâCommand Register ...................................................................... 387
10.9.3 STSâDevice Status............................................................................... 388
10.9.4 RIDâRevision ID .................................................................................. 389
10.9.5 CCâClass Codes................................................................................... 389
10.9.6 CLSâCache Line Size ............................................................................ 389
10.9.7 MLTâMaster Latency Timer.................................................................... 390
10.9.8 HTYPEâHeader Type............................................................................. 390
10.9.9 BISTâBuilt In Self Test ......................................................................... 390
10.9.10KTIBAâKT IO Block Base Address........................................................... 391
10.9.11KTMBAâKT Memory Block Base Address .................................................. 391
10.9.12RSVDâReserved .................................................................................. 392
10.9.13RSVDâReserved .................................................................................. 392
10.9.14RSVDâReserved .................................................................................. 392
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Datasheet
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