AC82G41SLGQ3 Datasheet, PDF (30/604 Pages) Intel Corporation – Intel® 4 Series Chipset Family

Introduction
1.2
1.2.1
(G)MCH System Overview
The (G)MCH was designed for use with the Intel^® Core™2 Extreme processor QX9000
series, Intel^® Core™2 Quad processor Q9000 series, and Intel^® Core™2 Duo processor
E8000 and E7000 series in the LGA775 Land Grid Array Package targeted for desktop
platforms. The role of a (G)MCH in a system is to manage the flow of information
between its interfaces: the processor interface, the System Memory interface, the
External Graphics or PCI Express interface, internal graphics interfaces, and the I/O
Controller through DMI interface. This includes arbitrating between the interfaces when
each initiates transactions. It supports one or two channels of DDR2 or DDR3 SDRAM.
It also supports PCI Express based external graphics and devices. The Intel 4 Series
Chipset platform supports the tenth generation I/O Controller Hub 10 (ICH10) to
provide I/O related features. Note that the Intel G41 Chipset supports the I/O
Controller Hub 7 (ICH7).
Host Interface
The (G)MCH supports a single LGA775 socket processor. The (G)MCH supports a FSB
frequency of 800, 1066, 1333 MHz. Host-initiated I/O cycles are decoded to PCI
Express, DMI, or the (G)MCH configuration space. Host-initiated memory cycles are
decoded to PCI Express, DMI, or system memory. PCI Express device accesses to non-
cacheable system memory are not snooped on the host bus. Memory accesses initiated
from PCI Express using PCI semantics and from DMI to system SDRAM will be snooped
on the host bus.
Processor/Host Interface (FSB) Details
• Supports Intel^® Core™2 Extreme processor QX9000 series, Intel^® Core™2 Quad
processor Q9000 series, and Intel^® Core™2 Duo processor E8000 and E7000 series
Family processors
• Supports Front Side Bus (FSB) at the following Frequency Ranges:
— 800, 1066, 1333 MT/s. FSB speeds are processor dependent.
• Supports FSB Dynamic Bus Inversion (DBI)
• Supports 36-bit host bus addressing, allowing the processor to access the entire
64 GB of the host address space.
• Has a 12-deep In-Order Queue to support up to twelve outstanding pipelined
address requests on the host bus
• Has a 1-deep Defer Queue
• Uses GTL+ bus driver with integrated GTL termination resistors
• Supports a Cache Line Size of 64 bytes
30
Datasheet