AC82G41SLGQ3 Datasheet, PDF (152/604 Pages) Intel Corporation – Intel® 4 Series Chipset Family

DRAM Controller Registers (D0:F0)
5.2.34
EPDCYCTRKWRTPRE—EPD CYCTRK WRT PRE
B/D/F/Type:
Address Offset:
Default Value:
Access:
Size:
0/0/0/MCHBAR
A19-A1Ah
0000h
R/W, RO
16 bits
Bit
Access
15:11
R/W
10:6
R/W
5:2
R/W
1:0
RO
Default
Value
00000b
00000b
0000b
00b
RST/PWR
Description
Core
Core
Core
Core
ACT To PRE Delayed (C0sd_cr_act_pchg): This field
indicates the minimum allowed spacing (in DRAM clocks)
between the ACT and PRE commands to the same rank-
bank.
Write To PRE Delayed (C0sd_cr_wr_pchg): This field
indicates the minimum allowed spacing (in DRAM clocks)
between the WRITE and PRE commands to the same rank-
bank.
READ To PRE Delayed (C0sd_cr_rd_pchg): This field
indicates the minimum allowed spacing (in DRAM clocks)
between the READ and PRE commands to the same rank-
bank.
Reserved
5.2.35
EPDCYCTRKWRTACT—EPD CYCTRK WRT ACT
B/D/F/Type:
Address Offset:
Default Value:
Access:
Size:
0/0/0/MCHBAR
A1C-A1Fh
00000000h
RO, R/W
32 bits
Bit
31:21
20:17
16:13
12:9
8:0
Access
RO
R/W
R/W
RO
R/W
Default
Value
RST/PWR
Description
000h
0000b
0000b
0h
000000000b
Core
Core
Core
Core
Core
Reserved
ACT to ACT Delayed (C0sd_cr_act_act[): This field
indicates the minimum allowed spacing (in DRAM clocks)
between two ACT commands to the same rank.
PRE to ACT Delayed (C0sd_cr_pre_act): This field
indicates the minimum allowed spacing (in DRAM clocks)
between the PRE and ACT commands to the same rank-
bank:12:9R/W0000bPRE-ALL to ACT Delayed
(C0sd_cr_preall_act):. This configuration register
indicates the minimum allowed spacing (in DRAM clocks)
between the PRE-ALL and ACT commands to the same
rank.
Reserved
REF to ACT Delayed (C0sd_cr_rfsh_act): This field
indicates the minimum allowed spacing (in DRAM clocks)
between REF and ACT commands to the same rank.
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