AC82G41SLGQ3 Datasheet, PDF (270/604 Pages) Intel Corporation – Intel® 4 Series Chipset Family

Host-Secondary PCI Express* Bridge Registers (D6:F0) (Intel^® 82P45 MCH Only)
8.52
VC0RCTL—VC0 Resource Control
B/D/F/Type:
Address Offset:
Default Value:
Access:
Size:
0/6/0/MMR
114–117h
800000FFh
RO, RW
32 bits
This register controls the resources associated with PCI Express Virtual Channel 0.
Bit
31
30:27
26:24
23:20
19:17
16:8
7:1
0
Access
RO
RO
RO
RO
RW
RO
RW
RO
Default
Value
1b
0h
000b
0000h
000b
00h
7Fh
1b
RST/
PWR
Core
Core
Core
Core
Core
Core
Core
Core
Description
VC0 Enable (VC0E): For VC0, this is hardwired to 1 and read only as
VC0 can never be disabled.
Reserved
VC0 ID (VC0ID): This field assigns a VC ID to the VC resource. For
VC0 this is hardwired to 0 and read only.
Reserved
Port Arbitration Select: This field configures the VC resource to
provide a particular Port Arbitration service. This field is valid for
RCRBs, Root Ports that support peer to peer traffic, and Switch Ports,
but not for PCI Express Endpoint devices or Root Ports that do not
support peer to peer traffic.
The permissible value of this field is a number corresponding to one of
the asserted bits in the Port Arbitration Capability field of the VC
resource.
Reserved
TC/VC0 Map (TCVC0M): This field indicates the TCs (Traffic
Classes) that are mapped to the VC resource. Bit locations within this
field correspond to TC values. For example, when bit 7 is set in this
field, TC7 is mapped to this VC resource. When more than one bit in
this field is set, it indicates that multiple TCs are mapped to the VC
resource. To remove one or more TCs from the TC/VC Map of an
enabled VC, software must ensure that no new or outstanding
transactions with the TC labels are targeted at the given Link.
TC0/VC0 Map (TC0VC0M): Traffic Class 0 is always routed to VC0.
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Datasheet