AC82G41SLGQ3 Datasheet, PDF (395/604 Pages) Intel Corporation – Intel® 4 Series Chipset Family

Intel^® Manageability Engine Subsystem Registers
10.9.22 PID—PCI Power Management Capability ID
B/D/F/Type:
Address Offset:
Default Value:
Access:
Size:
0/3/3/PCI
C8-C9h
D001h
RO
16 bits
See register definitions below.
Bit
15:8
7:0
Access
RO
RO
Default
Value
D0h
01h
RST/PWR
Description
Core
Core
Next Capability (NEXT): A value of D0h points to the
MSI capability.
Cap ID (CID): This field indicates that this pointer is a
PCI power management.
10.9.23 PC—PCI Power Management Capabilities
B/D/F/Type:
Address Offset:
Default Value:
Access:
Size:
0/3/3/PCI
CA-CBh
0023h
RO
16 bits
This register implements the power management capabilities of the function.
Bit
15:11
10
9
8:6
5
4
3
2:0
Access
RO
RO
RO
RO
RO
RO
RO
RO
Default
Value
00000b
0b
0b
000b
1b
0b
0b
011b
RST/PWR
Description
Core
Core
Core
Core
Core
Core
Core
Core
PME Support (PME): This field indicates no PME# in the
PT function.
D2 Support (D2S): The D2 state is not Supported
D1 Support (D1S): The D1 state is not supported
Aux Current (AUXC): PME# from D3 (cold) state is not
supported; therefore, this field is 000b.
Device Specific Initialization (DSI): This bit indicates
that no device-specific initialization is required.
Reserved
PME Clock (PMEC): This bit indicates that PCI clock is not
required to generate PME#
Version (VS): This field indicates support for the PCI
Power Management Specification, Revision 1.2.
Datasheet
395