AC82G41SLGQ3 Datasheet, PDF (565/604 Pages) Intel Corporation – Intel® 4 Series Chipset Family

Electrical Characteristics
Table 51. DC Characteristics
Symbol
Parameter
Min
Nom
Max
Unit Notes
I_OH
Output High Current (CMOS
Outputs)
6.2
8
9.8
mA
@V_{OH_}
HI ^min
V_OL
Output Low Voltage (CMOS
Outputs)
—
0
—
V
V_OH
Output High Voltage (CMOS
Outputs)
0.62
0.8
0.98
V
PWROK, CL_PWROK, RSTIN#
V_IL
V_IH
I_LEAK
C_IN
CL_RST#
Input Low Voltage
Input High Voltage
Input Leakage Current
Input Capacitance
1.05
1.93
50
477.292
1.081
2.011
75
503.396
1.122
V
2.093
V
120
μA
531.486
fF
V_IL
V_IH
I_LEAK
C_IN
ICH_SYNCB
Input Low Voltage
Input High Voltage
Input Leakage Current
Input Capacitance
VSS
—
Vref – 80 mV
V
Vref + 80mV
—
VCC
V
—
—
±20
μA
—
—
2.0
pF
I_OL
Output Low Current (CMOS
Outputs)
—
—
2.0
mA
@V_{OL_}
HI ^max
I_OH
Output High Current (CMOS
Outputs)
-2.0
—
—
mA
@V_{OH_}
HI ^min
V_OL
Output Low Voltage (CMOS
Outputs)
—
—
0.33
V
V_OH
Output High Voltage (CMOS
Outputs)
2.97
—
—
V
CRT_HSYNC, CRT_VSYNC
I_OL
Output Low Current (CMOS
Outputs)
—
I_OH
Output High Current (CMOS
Outputs)
—
V_OL
Output Low Voltage (CMOS
Outputs)
0
—
—
mA
@V_{OL_}
HI ^max
—
—
mA
@V_{OH_}
HI ^min
—
0.5@ 8mA
V
V_OH
Output High Voltage (CMOS
Outputs)
2.4 – 8mA
—
3.6
V
NOTES:
1. Determined with 2x (G)MCH Buffer Strength Settings into a 50 to 0.5xVCC_DDR test load.
2. Applies to pin to VCC or VSS leakage current for the DDR_A_DQ_63:0 and DDR_B_DQ_63:0 signals.
3. Applies to pin to pin leakage current between DDR_A_DQS_7:0, DDR_A_DQSB_7:0, DDR_B_DQS_7:0, and DDR_B_DQSB_7:0
signals.
4. Specified at the measurement point into a timing and voltage compliance test load as shown in Transmitter compliance eye diagram
of PCI Express* specification and measured over any 250 consecutive TX Uls.
5. Specified at the measurement point over any 250 consecutive Uls. The test load shown in Receiver compliance eye diagram of PCI
Express* spec should be used as the RX device when taking measurements.
6. Crossing voltage defined as instantaneous voltage when rising edge of BCLK0 equals falling edge of BCLK1.
7. V_Havg is the statistical average of the VH measured by the oscilloscope.
8. The crossing point must meet the absolute and relative crossing point specifications simultaneously. Refer to the appropriate
processor datasheet for further information.
Datasheet
565