AC82G41SLGQ3 Datasheet, PDF (36/604 Pages) Intel Corporation – Intel® 4 Series Chipset Family

Signal Description
2.1
Note:
Host Interface Signals
Unless otherwise noted, the voltage level for all signals in this interface is tied to the
termination voltage of the Host Bus (V_TT).
Signal Name
FSB_ADSB
FSB_BNRB
FSB_BPRIB
FSB_BREQ0B
FSB_CPURSTB
FSB_DBSYB
FSB_DEFERB
FSB_DINVB_[3:0]
FSB_DRDYB
Type
Description
I/O
GTL+
Address Strobe: The processor bus owner asserts FSB_ADSB
to indicate the first of two cycles of a request phase. The
(G)MCH can assert this signal for snoop cycles and interrupt
messages.
I/O
GTL+
Block Next Request: Used to block the current request bus
owner from issuing new requests. This signal is used to
dynamically control the processor bus pipeline depth.
O
GTL+
Priority Agent Bus Request: The (G)MCH is the only Priority
Agent on the processor bus. It asserts this signal to obtain the
ownership of the address bus. This signal has priority over
symmetric bus requests and will cause the current symmetric
owner to stop issuing new transactions unless the FSB_LOCKB
signal was asserted.
O
GTL+
Bus Request 0: The (G)MCH pulls the processor bus’
FSB_BREQ0B signal low during FSB_CPURSTB. The processors
sample this signal on the active-to-inactive transition of
FSB_CPURSTB. The minimum setup time for this signal is 4
HCLKs. The minimum hold time is 2 HCLKs and the maximum
hold time is 20 HCLKs. FSB_BREQ0B should be tri-stated after
the hold time requirement has been satisfied.
O
GTL+
CPU Reset: The FSB_CPURSTB pin is an output from the
(G)MCH. The (G)MCH asserts FSB_CPURSTB while RSTINB
(PCIRST# from the ICH) is asserted and for approximately
1 ms after RSTINB is de-asserted. The FSB_CPURSTB allows
the processor to begin execution in a known state.
I/O
GTL+
Data Bus Busy: Used by the data bus owner to hold the data
bus for transfers requiring more than one cycle.
O
GTL+
Defer: Signals that the (G)MCH will terminate the transaction
currently being snooped with either a deferred response or
with a retry response.
I/O
GTL+ 4x
Dynamic Bus Inversion: Driven along with the
FSB_DB_[63:0] signals. Indicates if the associated signals are
inverted or not. FSB_DINVB_[3:0] are asserted such that the
number of data bits driven electrically low (low voltage) within
the corresponding 16 bit group never exceeds 8.
FSB_DINVB_x Data Bits
FSB_DINVB_3
FSB_DB_[63:48]
FSB_DINVB_2
FSB_DB_[47:32]
FSB_DINVB_1
FSB_DB_[31:16]
FSB_DINVB_0
FSB_DB_[15:0]
I/O
GTL+
Data Ready: Asserted for each cycle that data is transferred.
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Datasheet