AC82G41SLGQ3 Datasheet, PDF (159/604 Pages) Intel Corporation – Intel® 4 Series Chipset Family

DRAM Controller Registers (D0:F0)
Bit
Access
Default
Value
RST/PWR
Description
0
RS/WC
0b
Core
In Use (IU): Software semaphore bit.
After a full (G)MCH RESET, a read to this bit returns a 0.
After the first read, subsequent reads will return a 1.
A write of a 1 to this bit will reset the next read value to 0.
Writing a 0 to this bit has no effect.
Software can poll this bit until it reads a 0, and will then
own the usage of the thermal sensor.
This bit has no other effect on the hardware, and is only
used as a semaphore among various independent software
threads that may need to use the thermal sensor.
Software that reads this register but does not intend to
claim exclusive access of the thermal sensor must write a
one to this bit if it reads a 0, in order to allow other
software threads to claim it.
See also THERM3 bit 7 and IUB, which are independent
additional semaphore bits.
5.2.42
TSC2—Thermal Sensor Control 2
B/D/F/Type:
Address Offset:
Default Value:
Access:
Size:
0/0/0/MCHBAR
CD9h
00h
R/W/L, RO
8 bits
This register controls the operation of the thermal sensor.
All bits in this register are reset to their defaults by MPWROK.
Datasheet
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