AC82G41SLGQ3 Datasheet, PDF (374/604 Pages) Intel Corporation – Intel® 4 Series Chipset Family

Intel^® Manageability Engine Subsystem Registers
10.6.22 IDECR—IDE Command Register
B/D/F/Type:
Address Offset:
Default Value:
Access:
Size:
0/3/2/IDE IO BAR0
7h
00h
R/W/V
8 bits
Reset: Host system Reset and D3->D0 transition
This register implements the Command register of the command block of the IDE
function. This register can be written only by the Host.
When the HOST reads the same address it reads the Status register DEV0 if DEV=0 or
Status Register DEV1 if DEV=1 (Drive/Head register bit [4]).
Bit
Access
Default
Value
RST/PWR
Description
7:0
R/W/V
00h
Core
IDE Command Data (IDECD): Host sends the
commands (read/ write, etc.) to the drive via this register.
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Datasheet