AC82G41SLGQ3 Datasheet, PDF (354/604 Pages) Intel Corporation – Intel® 4 Series Chipset Family

Intel^® Manageability Engine Subsystem Registers
10.5.11 SCTLBA—Secondary Control Block base Address
B/D/F/Type:
Address Offset:
Default Value:
Access:
Size:
0/3/2/PCI
1C-1Fh
00000001h
RO, R/W
32 bits
Reset: Host System Reset or D3->D0 transition
This 4-byte I/O space is used in Native Mode for Secondary Controller's Control block.
Secondary Channel is not implemented and reads return 7F7F7F7Fh and all writes are
ignored.
Bit
31:16
15:2
1
0
Access
RO
R/W
RO
RO
Default
Value
0000h
0000h
0b
1b
RST/PWR
Description
Core
Core
Core
Core
Reserved
Base Address (BAR): Base Address of the I/O space (4
consecutive I/O locations).
Reserved
Resource Type Indicator (RTE): This bit indicates a
request for I/O space.
10.5.12 LBAR—Legacy Bus Master Base Address
B/D/F/Type:
Address Offset:
Default Value:
Access:
Size:
0/3/2/PCI
20-23h
00000001h
RO, R/W
32 bits
Reset: Host system Reset or D3->D0 transition
This Bar is used to allocate I/O space for the SFF-8038i mode of operation (aka Bus
Master IDE).
Bit
31:16
15:4
3:1
0
Access
RO
R/W
RO
RO
Default
Value
0000h
000h
000b
1b
RST/PWR
Description
Core
Core
Core
Core
Reserved
Base Address (BA): Base Address of the I/O space (16
consecutive I/O locations).
Reserved
Resource Type Indicator (RTE): This bit indicates a
request for I/O space.
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