AC82G41SLGQ3 Datasheet, PDF (260/604 Pages) Intel Corporation – Intel® 4 Series Chipset Family

Host-Secondary PCI Express* Bridge Registers (D6:F0) (Intel^® 82P45 MCH Only)
Bit
Access
Default
Value
RST/
PWR
Description
10
RO
9:4
RO
3:0
RO
Undefined: The value read from this bit is undefined. In previous
0b
Core
versions of this specification, this bit was used to indicate a Link
Training Error. System software must ignore the value read from this
bit. System software is permitted to write any value to this bit.
Negotiated Link Width (NLW): Indicates negotiated link width.
This field is valid only when the link is in the L0 or L1 states (after link
width negotiation is successfully completed).
01h = x1
04h = ‘x4 — This is not a supported PCIe Gen2.0 link width. Link
00h
Core
width x4 is only valid when PCIe Gen1.1 I/O card is used in the
secondary port.
08h = x8 — This is not a supported PCIe Gen2.0 link width. Link
width x8 is only valid when PCIe Gen1.1 I/O card is used in the
secondary port.
10h = x16
All other encodings are reserved.
Current Link Speed (CLS): This field indicates the negotiated Link
speed of the given PCI Express Link.
Defined encodings are:
0h
Core 0001b = 5.0 GT/s PCI Express Link
0010b = 5 GT/s PCI Express Link
All other encodings are reserved. The value in this field is undefined
when the Link is not up.
260
Datasheet