AC82G41SLGQ3 Datasheet, PDF (434/604 Pages) Intel Corporation – Intel® 4 Series Chipset Family

Intel^® Virtualization Technology for Directed I/O Registers (D0:F0) (Intel^® 82Q45 GMCH Only)
Bit
Access
Default
Value
RST/PWR
Description
28
RO
Enable Advanced Fault Logging (EAFL): This field is
valid only for implementations supporting advanced fault
logging. If advanced fault logging is not supported, writes
to this field are ignored. Software writes to this field to
request hardware to enable or disable advanced fault
logging.
0 = Disable advanced fault logging. In this case,
translation faults are reported through the Fault
Recording registers.
1 = Enable use of memory-resident fault log. When
0b
Core
enabled, translation faults are recorded in the
memory-resident log. The fault log pointer must be set
in hardware (through SFL field) before enabling
advanced fault logging.
Hardware reports the status of the advanced fault logging
enable operation through the AFLS field in the Global
Status register.
Value returned on read of this field is undefined.
27
W
26
RO
NOTE: This field is reserved as this feature is not
supported.
Write Buffer Flush (WBF): This bit is valid only for
implementations requiring write buffer flushing. If write
buffer flushing is not required, writes to this field are
ignored.
Software sets this field to request hardware to flush the
root-complex internal write buffers. This is done to ensure
any updates to the memory-resident DMA-remapping
0b
Core
structures are not held in any internal write posting
buffers. Refer to Section 9.1 for details on write-buffer
flushing requirements.
Hardware reports the status of the write buffer flushing
operation through the WBFS field in the Global Status
register.
Clearing this bit has no effect. Value returned on read of
this field is undefined.
Queued Invalidation Enable (QIE): This field is valid
only for implementations supporting queued invalidations.
Software writes to this field to enable or disable queued
invalidations.
0 = Disable queued invalidations.
0b
Core
1 = Enable use of queued invalidations.
Hardware reports the status of queued invalidation enable
operation through QIES field in the Global Status register.
The value returned on a read of this field is undefined.
NOTE: This field is reserved as this feature is not
supported.
434
Datasheet