AC82G41SLGQ3 Datasheet, PDF (313/604 Pages) Intel Corporation – Intel® 4 Series Chipset Family

Integrated Graphics Registers (Device 2) (Intel^® 82Q45, 82Q43, 82B43, 82G45, 82G43, 82G41
GMCH Only)
9.2.26
PMCS—Power Management Control/Status
B/D/F/Type:
Address Offset:
Default Value:
Access:
Size:
0/2/1/PCI
D4-D5h
0000h
RO, R/W
16 bits
Bit
15
14:13
12:9
8
7:2
1:0
Access
RO
RO
RO
RO
RO
R/W
Default
Value
0b
00b
0h
0b
00h
00b
RST/
PWR
Description
Core
Core
Core
Core
Core
FLR, Core
PME Status (PMESTS): This bit is 0 to indicate that IGD does
not support PME# generation from D3 (cold).
Data Scale (DSCALE): The IGD does not support data register.
This bit always returns 0 when read, write operations have no
effect.
Data Select (DATASEL): The IGD does not support data
register. This bit always returns 0 when read, write operations
have no effect.
PME Enable (PME_EN): This bit is 0 to indicate that PME#
assertion from D3 (cold) is disabled.
Reserved
Power State (PWRSTAT): This field indicates the current power
state of the IGD and can be used to set the IGD into a new power
state. If software attempts to write an unsupported state to this
field, write operation must complete normally on the bus, but the
data is discarded and no state change occurs. On a transition
from D3 to D0 the graphics controller is optionally reset to initial
values.
00 = Default
01 = D1 (Not Supported)
10 = D2 (Not Supported)
11 = D3
9.2.27 SWSMI—Mirror of Func0 Software SMI
B/D/F/Type:
Address Offset:
Default Value:
Access:
Size:
0/2/1/PCI
E0-E1h
0000h
RO
16 bits
Since there is the potential that DVO port legacy drivers exist that expect this register
at this address, Device 2, Function 0, address E0h–E1h is reserved for this register.
Bit
15:8
7:1
0
Access
RO
RO
Default
Value
00h
00h
RO
0b
RST/
PWR
Core
Core
Core
Description
Software Scratch Bits (SWSB):
Software Flag (SWF): Used to indicate caller and SMI function
desired, as well as return result.
GMCH Software SMI Event (GSSMIE): When Set, this bit will
trigger an SMI. Software must write a 0 to clear this bit.
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Datasheet
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