AC82G41SLGQ3 Datasheet, PDF (495/604 Pages) Intel Corporation – Intel® 4 Series Chipset Family

Intel^® Virtualization Technology for Directed I/O Registers (D0:F0) (Intel^® 82Q45 GMCH Only)
12.3.3
ECAP_REG—Extended Capability Register
B/D/F/Type:
Address Offset:
Default Value:
Access:
Size:
0/2/0/GFXVTBAR
10-17h
0000000000001000h
RO
64 bits
the register reports DMA-remapping hardware extended capabilities.
Bit
63:24
23:20
19:18
17:8
7
6
Access
RO
RO
RO
RO
RO
RO
Default
Value
00000000h
0h
RST/PWR
Description
Core
Core
Reserved
Maximum Handle Mask Value (MHMV): The value in
this field indicates the maximum supported value for the
Handle Mask (HM) field in the interrupt entry cache
invalidation descriptor (iec_inv_dsc).
This field is valid only when the IR field is reported as Set.
00b
010h
0b
Core
Core
Core
NOTE: This field is reserved as this feature is not
supported.
Reserved
Invalidation Unit Offset (IVO): This field specifies the
location to the first
IOTLB invalidation unit relative to the register
base address of this DMA-remapping hardware
unit.
If the register base address is X, and the value
reported in this field is Y, the address for the
first IOTLB invalidation unit is calculated as
X+(16*Y).
If N is the value reported in NIU field, the
address for the last IOTLB invalidation unit is
calculated as X+(16*Y)+(16*N).
Snoop Control (SC):
0 = Hardware does not support 1-setting of the SNP field
in the page-table entries.
1 = Hardware supports the 1-setting of the SNP field in the
page-table entries.
NOTE: This field is reserved as this feature is not
supported.
Pass Through (PT):
0 = Hardware does not support pass through translation
type in context entries.
0b
Core
1 = Hardware supports pass-through translation type in
context entries.
NOTE: This field is reserved as this feature is not
supported.
Datasheet
495