AC82G41SLGQ3 Datasheet, PDF (553/604 Pages) Intel Corporation – Intel® 4 Series Chipset Family

Functional Description
13.11
Clocking
The (G)MCH has a total of 5 PLLs providing many times that many internal clocks. The
PLLs are:
• Host PLL – Generates the main core clocks in the host clock domain. Can also be
used to generate memory and internal graphics core clocks. Uses the Host clock
(H_CLKIN) as a reference.
• Memory I/O PLL - Optionally generates low jitter clocks for memory I/O interface,
as opposed to from Host PLL. Uses the Host FSB differential clock (HPL_CLKINP/
HPL_CLKINN) as a reference. Low jitter clock source from memory I/O PLL is
required for DDR667 and higher frequencies.
• PCI Express PLL – Generates all PCI Express related clocks, including the Direct
Media that connect to the ICH. This PLL uses the 100 MHz clock (EXP_CLKNP/
EXP2_CLKNP) as a reference. Display PLL A – Generates the internal clocks for
Display A. Uses D_REFCLKIN as a reference.
• Display PLL B – Generates the internal clocks for Display B. Also uses D_REFCLKIN
as a reference.
CK505 is the clocking chip required for the platform.
Datasheet
553