AC82G41SLGQ3 Datasheet, PDF (132/604 Pages) Intel Corporation – Intel® 4 Series Chipset Family

DRAM Controller Registers (D0:F0)
5.2.9
C0CYCTRKACT—Channel 0 CYCTRK ACT
B/D/F/Type:
Address Offset:
Default Value:
Access:
Size:
0/0/0/MCHBAR
252-255h
00000000h
R/W, RO
32 bits
This register is for Channel 0 CYCTRK Activate.
Bit
31:30
Access
RO
29
R/W
28
R/W
27:22
R/W
21
R/W
20:17
R/W
16:13
R/W
Default
Value
0h
0b
0b
000000b
0b
0000b
0000b
RST/PWR
Description
Core
Core
Core
Core
Core
Core
Core
Reserved
FAW Windowcnt Bug Fix Disable
(C0sd_cr_cyctrk_faw_windowcnt_fix_disable): This
configuration register disables the CYCTRK FAW windowcnt
bug fix.
1 = Disable CYCTRK FAW windowcnt bug fix
0 = Enable CYCTRK FAW windowcnt bug fix
FAW Phase Bug Fix Disable
(C0sd_cr_cyctrk_faw_phase_fix_disable): This
configuration register disables the CYCTRK FAW phase
indicator bug fix.
1 = Disable CYCTRK FAW phase indicator bug fix
0 = Enable CYCTRK FAW phase indicator bug fix
ACT Window Count (C0sd_cr_act_windowcnt): This
configuration register indicates the window duration (in
DRAM clocks) during which the controller counts the # of
activate commands which are launched to a particular
rank. If the number of activate commands launched within
this window is greater than 4, then a check is implemented
to block launch of further activates to this rank for the rest
of the duration of this window.
Max ACT Check (C0sd_cr_maxact_dischk): This
configuration register enables the check which ensures
that there are no more than four activates to a particular
rank in a given window.
ACT to ACT Delayed (C0sd_cr_act_act[): This
configuration register indicates the minimum allowed
spacing (in DRAM clocks) between two ACT commands to
the same rank. This field corresponds to tRRD in the DDR
Specification.
PRE to ACT Delayed (C0sd_cr_pre_act): This
configuration register indicates the minimum allowed
spacing (in DRAM clocks) between the PRE and ACT
commands to the same rank-bank:12:9R/W0000bPRE-ALL
to ACT Delayed (C0sd_cr_preall_act):This configuration
register indicates the minimum allowed spacing (in DRAM
clocks) between the PRE-ALL and ACT commands to the
same rank. This field corresponds to tRP in the DDR
Specification.
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Datasheet