AC82G41SLGQ3 Datasheet, PDF (28/604 Pages) Intel Corporation – Intel® 4 Series Chipset Family

Introduction
Term
IGD
INTx
Intel^® ICH10
Intel^® ICH7
IOQ
LCD
LVDS
MCH
MSI
OOQ
PAVP
PCI Express*
Primary PCI
Processor
Rank
SCI
SDVO
SDVO Device
SERR
SMI
TMDS
Description
Internal Graphics Device
An interrupt request signal where X stands for interrupts A, B, C and D
Tenth generation I/O Controller Hub component that contains the primary PCI
interface, LPC interface, USB2.0, SATA, and other I/O functions.
Seventh generation I/O Controller Hub component that contains additional
functionality compared to previous Intel ICH components. ICH7 contains the
primary PCI interface, LPC interface, USB2, SATA, ATA-100, and other I/O
functions. It communicates with the (G)MCH over a proprietary interconnect
called DMI. For the 82G41 GMCH, the term Intel ICH in this document refers
to the ICH7.
In Order Queue
Liquid Crystal Display
Low Voltage Differential Signaling. A high speed, low power data transmission
standard used for display connections to LCD panels.
Memory Controller Hub component that contains the processor interface,
DRAM controller, and PCI Express port. The MCH communicates with the I/O
controller hub over the DMI interconnect.
Message Signaled Interrupt. A transaction conveying interrupt information to
the receiving agent through the same path that normally carries read and
write commands.
Out of Order Queueing
Protected Audio-Video Path for supporting secure playback of Intel HD Audio
and Video content
A high-speed serial interface whose configuration is software compatible with
the legacy PCI specifications.
The physical PCI bus that is driven directly by the ICH10/ICH7 component.
Communication between Primary PCI and the (G)MCH occurs over DMI. The
Primary PCI bus is not PCI Bus 0 from a configuration standpoint.
Refers to the microprocessor that connects to chipset through the FSB
interface on the (G)MCH.
A unit of DRAM corresponding to eight x8 SDRAM devices in parallel or four
x16 SDRAM devices in parallel, ignoring ECC. These devices are usually, but
not always, mounted on a single side of a DIMM.
System Control Interrupt. Used in ACPI protocol.
Serial Digital Video Out (SDVO). Digital display channel that serially transmits
digital display data to an external SDVO device. The SDVO device accepts this
serialized format and then translates the data into the appropriate display
format (i.e., TMDS, LVDS, and TV-Out). This interface is not electrically
compatible with the previous digital display channel - DVO. The SDVO
interface is multiplexed on a portion of the x16 graphics PCI Express interface.
Third party codec that uses SDVO as an input. The device may have a variety
of output formats, including DVI, LVDS, HDMI, TV-out, etc.
System Error. An indication that an unrecoverable error has occurred on an
I/O bus.
System Management Interrupt. SMI is used to indicate any of several system
conditions such as thermal sensor events, throttling activated, access to
System Management RAM, chassis open, or other system state related
activity.
Transition Minimized Differential Signaling. Signaling interface from Silicon
Image that is used in DVI and HDMI.
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Datasheet